Computer aided design tools are utilized on a wide scale in many research and development environments to design electrical, mechanical, chemical and/or other types of products. In the field of semiconductor design, such CAD tools help designers implement complex circuit architectures into a semiconductor products. Such CAD tools are used for system level design, custom integrated circuit design tools, deep submicron design, logic design and verification, and PCB, package and interconnect design. A popular set of CAD tools, referred to as the Opus CAD design environment, is commercially available from Cadence Design Systems, Inc. of San Jose, Calif. In the Opus CAD design environment, the physical design of an integrated circuit depends on a set of design rules. The design rules are often determined inherently from the type of semiconductor fabrication technology, e.g., CMOS, NMOS, PMOS, etc. which is being utilized to implement the integrated circuit. Design rules typically define physical parameters and relationships such as minimum area, diagonal width, diagonal space, etc., of a physical entity in an integrated circuit. Throughout the development and design of an integrated circuit, such design rules are referenced directly and indirectly by both commercial CAD design tools and custom designed tools developed in-house by the designers. Such custom designed tools may be used to create designs, check designs for rule violations, or to preprocess/post process a design to/from other design tools. A subset of all the design rules in the Opus environment are stored in an internal file referred to as a “technology” file. The technology file is used internally by the Opus CAD tool products.
In an Opus design environment, custom designed CAD tools may be written in the SKILL programming language. The SKILL programming language is a high level language with primitives and operators specifically designed for CAD related tasks. Traditionally, custom CAD tools have been written to contain hard-coded numbers which comply with the design rule parameters for a particular technology. Subsequent changes in design rules, e.g. a change in a minimum width from a value of 0.30 to a value of 0.36, requires that all custom CAD tools likewise be updated accordingly. A custom designed CAD tool, however, may have the same numeric value hard coded multiple times within the tool, not all of which are associated with the design rule parameter to be updated. Accordingly the task of updating design rules becomes time consuming and is prone to errors. In addition, if a large number of custom CAD tools are utilized by the circuit designers, as is common, the task of maintaining all custom CAD tools in synchronization with the current set of design rules becomes even more impractical. Further, errors are propagated when the results of one custom designed CAD tool utilizes the results of other custom CAD tool which was not updated or updated erroneously. In addition, many custom CAD tools must be essentially rewritten when extensive design rule changes occurs, such as with implementation of a design with a different technology.
Accordingly, a need exists for a technique in which CAD tools in a design environment may be synchronized and updated efficiently with a current set of design rules.
An additional need exists for a technique in which SKILL program tools may be synchronized with one or more design rules in an Opus CAD environment through.